Project log/status at a glance. This is a personal blog, not a technical one, so will not be submitted. An actual 'lab book' is(will be ) here A project plan/timeline is (will be) here.
October 26 2010: Been a bit on and off. Mostly off. Completed a demo of the UART . That is captured and zipped into repositry. To get project on track, will look at using UART to squirt in static data (but at 'real time' rates) into thing, as this will save a lot of work that is (literally 'academic' - i.e. serial data is more or less format of ADC out put, so surely is quite defensible to use a PC to emulate ADC?....
March 25 2010: Started UART (External ports and internal signals defined). The design is a bit of a cheat, as I am going to make a baud generator each for TX and RX, and these will actually do a bit more (clock the state machines, rather than strobe the bits)
March 23 2010: Doh! Actually put the interim report into the repositry. Ran out of fag packets, so have no stationary to design with. Consider taking up smoking so this doesn't happen again. Will either use computer or paper instead. Broke project into more distinct, testable sections. This is is loosely put into timeline.
March 21 2010: No comments received on Interim report. Submitted release interim report (Added conclusions to draft)
March 12 2010: Submitted draft Interim Report
March, 2010: Sorry, did I blink for a very long time there?. Was supposed to have interim report finished by Dec/early Jan. Got a bit distracted by all that business in Shipley.!. Interinm report is now finished, in repositry, and will be submitted after final proof reading, thursday.
8 December 2009 : Continuing work on interim report. ' Step over 'medical bit until speak to D.H. , proceded with extracting block diagram from Quartus, selecting dev kit,language, etc.
5 December 2009 : Reversed time line so latest stuff is at top!!
4 December 2009 : Happy with architecture. Was definitely the right way to go! Internal and external interfaces defined, all main entities defined ( as ports)].
Note : there is some code in some of the blocks. some of this is illustrative, some is inherited from earlier tests, some was just written at the time to capture an idea.
20 nov - 4 december 2009 : Discontinued earlier work on individual blocks (e..g VGA driver, etc) . Focused on design all top level architecture, interfaces, general system level stuff.
7- 19 Nov Some low level design activity, a VGA driver (translated to VHDL from the verilog example in AMI4460 worked example)
A test build including a 512 point, 16 bit FFT uses 32% of the device on the DE1 board, so that is taken to indicate the design will fit.
Spent some time remembering how VHDL works, and re-took my pledge of obesiance to the type conventions. Reminded myself why I selected VHDL
Selected VHDL as language to use. A purely personal choice, because Verilog taste a bit like C, which I use extensively elsewhere, use VHDLto force a different mind set.
5 October 2009 looking to start this project again.
